1. Field of the Invention
The present invention relates to a demodulation apparatus used in a data receiving apparatus, and in particular to a demodulation apparatus for compensating for a frequency drift of a digital modulation signal.
2. Description of the Related Art
Recently, implementation of digital video broadcasting has been discussed in both the terrestrial and satellite broadcasting. In digital video broadcasting, digital modulation signals are used, and thus a demodulation apparatus for demodulating the digital modulation signal is required.
Demodulation apparatuses for demodulating the modulation signal have two types of structures. In one type of structure, a digital modulation signal having various center frequencies is first converted into an IF signal of a frequency (f1) by a channel selection circuit, and then the IF signal of a frequency (f1) is digitally demodulated. In the other type of structure, the IF signal of a frequency (f1) obtained by the channel selection circuit is further converted into another IF signal of a frequency (f2), and then such an IF signal of a frequency (f2) is digitally demodulated.
For digital demodulation, a synchronization detector system is often used. In this system, a recovered carrier which is in synchronization with a carrier of the digital modulation signal is required. Such a recovered carrier is generally obtained by a carrier recovery circuit including a PLL circuit. In general, such a demodulation apparatus is often provided with an AFC function so as also to deal with a digital modulation signal which is input in the state of offsetting from a prescribed frequency by a certain frequency.
FIG. 35 is a block diagram of a conventional demodulation apparatus 500 including a channel selection circuit 110, a carrier recovery circuit 9, and an AFC circuit 20.
The channel selection circuit 110 includes a frequency converter 111, a voltage-controlled oscillator 112 (hereinafter, referred to as a "VCO"), a variable frequency divider 113, a reference oscillator 114, a phase comparator 115, a loop filter 116, and a microprocessor 117.
In the channel selection circuit 110, a frequency dividing ratio for the variable frequency divider 113 is set based on channel selection information which is input to the microprocessor 117. The frequency of the VCO 112 is divided by the frequency dividing ratio. A phase difference (phase error) between an output signal from the variable frequency divider 113 and an output signal from the reference oscillator 114 is detected by the phase comparator 115. The detected phase error is smoothed by the loop filter 116 and fedback as a control signal for the VCO 112. Thus, the VCO 112 performs oscillation stably at a frequency which is obtained by multiplying the frequency of the reference oscillator 114 by an integer. Such an integer corresponds to a frequency dividing ratio of the variable frequency divider 113.
A QPSK modulation signal which is input to the channel selection circuit 110 is processed with frequency conversion by the frequency converter 111 to be an IF signal. After an unnecessary spurious component is removed from the IF signal by a band-pass filter (hereinafter, referred to as a "BPF") 118, the IF signal is input to quadrature demodulator 1. The IF signal is then converted into an I baseband signal and a Q baseband signal based on an output signal from a local oscillator 2. The I baseband signal and the Q baseband signal have quadrature relationship to each other. The I and Q baseband signals which are generated as analog signals are converted into I and Q baseband signals each having a digital value by A/D converters 3 and 4, respectively. The digital I and Q baseband signals are treated with frequency conversion by an operating frequency of a digital VCO (hereinafter, referred to as a "DVCO") 6 by a complex multiplier 5 having a frequency conversion function. Then, the I and Q baseband signals respectively have waves thereof shaped by digital transversal filters (hereinafter, referred to as "DTFs") 7 and 8. The resultant signals are input to the carrier recovery circuit 9.
The carrier recovery circuit 9 includes a complex multiplier 11, a phase detector 12, a PLL loop filter 13 and a DVCO 14. These elements form a closed loop. The carrier recovery circuit 9 has a function of generating recovered carriers from the I and Q baseband signals which are input to the complex multiplier 11. When a phase locking is realized in the carrier recovery circuit 9, the recovered I and Q baseband signals are output.
The carrier recovery circuit 9 operates in the following manner.
The I and Q baseband signals which are input to the complex multiplier 11 having a phase rotation function are output after being treated with phase rotation by the DVCO 14 and are input to the phase detector 12. The phase detector 12 detects a phase difference between the input signal and a reference phase and outputs a signal indicating the detected difference (such a signal is referred to as a "phase error signal"). The phase error signal is smoothed by the PLL loop filter 13 and then input to the DVCO 14. The DVCO 14 outputs a recovered carrier which is in synchronization with the I and Q baseband signals to the complex multiplier 11. Accordingly, the complex multiplier 11 outputs recovered I and Q baseband signals which correspond to a transmitted data included in the QPSK modulation signal.
The AFC circuit 20 includes a frequency error detector 21, an AFC loop filter 22, and a latch circuit 23. The frequency error detector 21 detects a frequency error between the center frequency of the IF signal and the oscillation frequency of the local oscillator 2 based on the phase error signal sent from the phase detector 12. The frequency error signal is smoothed by the AFC loop filter 22 and input to the DVCO 6 via the latch circuit 23. By the frequency error signal, an operating frequency of the DVCO 6 is controlled to compensate for the frequency error. When the detected frequency error is less than a reference value, an AFC hold signal is supplied to the latch circuit 23 from the frequency error detector 21. By the AFC hold signal, data for controlling the oscillation frequency of the DVCO 6 is held by the latch circuit 23, and thus the DVCO 6 operates at a constant oscillation frequency. Moreover, when the detected frequency error is less than the reference value, an AFC/PLL loop switching signal is supplied to the PLL loop filter 13 from the frequency error detector 21 to operate the PLL loop filter 13. Thus, the carrier recovery circuit 9 pulls in a frequency error which cannot be removed by the AFC circuit 20 and compensates for such a frequency error. Simultaneously, a phase locking is established by the carrier recovery circuit 9, and the recovered I and Q baseband signals are output.
In satellite broadcasting, a dielectric resonator is generally used for a local oscillator of a BS converter. Accordingly, the frequency of the local oscillator often offsets from the desired frequency, for example, by several megahertz in an extreme case.
In the demodulation apparatus 500, in the case where a center frequency of the QPSK modulation signal which is input to the channel selection circuit 110 offsets from a prescribed frequency, the center frequency of the IF signal which is input to the quadrature demodulator 1 also offsets from the oscillation frequency of the local oscillator 2. When the offset frequency is larger than the frequency range which can be pulled in by the AFC circuit 20, the AFC circuit 20 does not operate normally. As a result, the carrier recovery circuit 9 cannot establish phase locking. Thus, data cannot be demodulated.
Even if the offset frequency of the IF signal with respect to the local oscillator 20 is smaller than the frequency range which can be pulled in by the AFC circuit 20 and thus the AFC circuit 20 is operable normally to realize data demodulation, the pull in time of the AFC circuit 20 increases as the offset frequency increases. Accordingly, as the offset frequency increases, a time period required for data to be correctly demodulated as measured from the start of channel selection performed by the channel selection circuit 110 becomes longer. Hereinafter, such a time period will be referred to as a "channel selection time period".
Even if the offset frequency of the IF signal with respect to the local oscillator 2 is smaller than the frequency which can be pulled in by the AFC circuit 20 and thus the AFC circuit 20 is operable normally to realize data demodulation, when the offset frequency is excessively large, the spectrum of the IF signal deviates from the center frequency of the BPF 118. In order to operate the demodulation apparatus 500 normally even in such circumstances, the bandwidth of the BPF 118 needs to be set broadly. However, by setting the bandwidth of the BPF 118 broadly, the ability of eliminating an interference signal on adjacent channels is lowered. Thus, an error rate of the demodulation apparatus 500 is deteriorated.